1. Field of the Invention
The present invention relates to a method for the making of the metallizations of a transistor with a vertical structure, having a raised pattern called a mesa: the deposition of the metallizations on and around the mesa should not touch the vertical flanks of the pattern so as to prevent short-circuiting because of unwanted deposits.
The method according to the invention can be applied preferably to vertical components of the III--V group and, more particularly, to heterojunction bipolar transistors (HBTs) in which the current is conveyed perpendicularly to the surface of the substrate: there is therefore at least one access electrode metallization (the emitter) on the mesa and one control electrode metallization (the base) at the foot of the mesa, the second access metallization (the collector) being in a third plane, either on the back of the substrate or at the bottom of an etching. To enable these transistors, which are designed for the microwave frequencies, to work efficiently, it is necessary to:
reduce the surface area of the base-collector junction to the maximum; PA1 prevent short-circuits between the emitter and the base; PA1 limit the interaction between the base of the transistor and the hydrogen coming from the etching plasma. PA1 an n doped substrate 1 used as a collector; PA1 a p.sup.+ doped layer 2 which constitutes the base; PA1 an n doped layer 3, which is the emitter, covered with an n.sup.+ doped layer 4 to improve the ohmic contact with the emitter metallization 5.
There are certain field-effect transistors, for example SISFETs (Semiconductor-Insulator-Semiconductor Field Effect Transistors) which, although the current therein flows in parallel to the surface of the substrate, may be considered to be vertical components inasmuch as they comprise an etched semiconductor pattern used to self-align two metallizations with respect to each other.
Furthermore, the method according to the invention is designed more particularly for power transistors in which the working temperature can reach 200.degree. C., which therefore means that the device should have very high thermal stability.
2. Description of the Prior Art
A method for the making of the metallizations of an HBT type vertical transistor is already described in the French patent application No. 90 12442, filed on 9th October by the present Applicant and corresponds to U.S. Pat. No. 5,194,403. This method is recalled briefly by means of FIG. 1.
The transistor described in this figure comprises:
The materials of these layers are all of the III--V group but those of the two layers 3 and 4 (GaInP for the layer 3 and GaAs for the layer 4 for example) are chosen so as to show a different reaction to two different etching methods: for example, the etching of the mesa 3+4+5 is done by a first reactive ion etching or RIE of chlorinated compounds in the presence of helium while a second RIE by methane in the presence of hydrogen creates a sub-etching of the contact layer 4 beneath the metallization 5.
The whole piece is covered with a layer 6+7+8 pf a dielectric, the parts 6 of which have a cavity that penetrates the sub-etching of the layer 4. This cavity will subsequently interrupt the parasitic metallizations that get deposited on the flanks of the mesa and that short-circuit the emitter and the base. A third ion etching with sulphur hexafluoride is used to eliminate the parts 7 and 8 of the dielectric which are deposited at the location of the emitter and base metallizations: an evaporation of metals will deposit the base contact at 8 and reinforce the emitter contact at 7.
This method is effective, but uses three operations of reactive ion etching: a more promising approach to the industrial-scale manufacture of HBT type transistors lies in implementing technological means that are simpler, less expensive and therefore more economical for the final product.